This invention relates to a semiconductor and, more particularly, to an ECL (Emitter Coupled Logic) integrated circuit.
Semiconductor integrated circuits using bipolar transistors for transmitting logic signals are generally classified into TTL circuits, ECL circuits, and others. In TTL circuits, high potential levels range from 2.4 V to 2.5 V, low potential levels range from 0 V to 0.4 V. In ECL circuits, potential levels are -0.7 V to -1.9 V, and amplitudes are around 1 V, which are largely different from those of TTL circuits and require different usages.
FIG. 4 is a circuit diagram of a conventional differential ECL circuit, and FIG. 5 is an explanatory diagram schematically showing potentials at internal nodes in the differential ECL circuit of FIG. 4 when the base-emitter voltage V.sub.BE of npn bipolar transistors is 0.9 V and the reference potential GND is 0 V.
Construction of the differential ECL circuit is explained below.
Resistors R1, R2 are supplied at their first ends with the reference potential GND, which is typically the ground potential. Connected to the other ends of the resistors R1 and R2 are collectors of npn bipolar transistors Q1 and Q2. Introduced to bases of these two npn bipolar transistors Q1, Q2 are input signals IN and /IN (/ denotes inverted signal) of potential levels between -0.9 V and -1.7 V. Commonly connected emitters of the npn bipolar transistors Q1, Q2 are connected to one end of a resistor R3, and the power source potential V.sub.EE is applied to the other end of the resistor R3. These elements form a current switch S1, and output from the current switch S1 is used as input to an emitter follower. That is, bases of npn bipolar transistors Q3, Q4 whose collectors are supplied with the reference potential GND are connected to the connection node of a resistor R1 and the collector of the npn bipolar transistor Q1 and the connection node of a resistor R2 and the collector of the npn bipolar transistor Q2. Emitters of the npn bipolar transistors Q3, Q4 are connected to given ends of resistors R4, R5 whose other ends are supplied with the power source potential V.sub.EE. Output signals OUT and /OUT of the differential ECL circuit are taken out from connection nodes of the npn bipolar transistors Q3, Q4 and given ends of resistors R4, R5. The resistors R1 and R2 have the same resistance value R.
In the conventional differential ECL circuit, input signals IN and /IN of potential levels from -0.9 V to -1.7 V are introduced to the current switch S1. Among two npn bipolar transistors Q1, Q2 forming the current switch S1, one having a higher base voltage is turned ON, and emitter potentials of Q1, Q2 represent values lower by corresponding base-emitter voltages V.sub.BE than the higher base potential.
The differential ECL circuit operates as explained below.
One of the resistors R1, R2 connected to one of the npn bipolar transistors Q1, Q2 currently in its ON state permits a current I to flow from a reference voltage point for giving the reference potential GND to one end, and the potential of its other end decreases to -R.sup.X I. Further, in the emitter follower, a potential -R.sup.X I-V.sub.BE which is lower than the potential -R.sup.X I by the base-emitter voltage V.sub.BE of the ON-state npn bipolar transistor Q3 or Q4 is taken out from the output terminal as an output signal OUT or /OUT of a LOW level. On the other hand, the other of the resistors R1, R2 connected to OFF-state one of the npn bipolar transistors Q1, Q2 does not introduce the current from the reference potential point for giving the reference potential GND to one end, and maintains a potential substantially equal to the reference potential GND at the other end. Therefore, in the emitter follower, a potential GND-V.sub.BE lower than the reference potential GND by the base-emitter voltage V.sub.BE of the ON-state npn bipolar transistor Q3 or Q4 is taken out from the output terminal as an output signal OUT or /OUT of a HIGH level.
As a result, when, for example, the base potential of the npn bipolar transistor Q1 is -0.9 V and the base potential of Q2 is -1.7 V, the npn bipolar transistor Q1 is turned ON, and emitter potentials of Q1, Q2 become -0.9 V-V.sub.BE =-1.8 V.
In the above-explained differential ECL circuit, however, when the base potential of the npn bipolar transistor Q1 is switched from -0.9 V to -1.7 V, and the base potential of Q2 from -1.7 V to -0.9, the base potential of Q1 and the base potential of Q2 transitionally becomes equal, and the emitter potentials of Q1 and Q2 decrease to -1.3 V-V.sub.BE =-2.2 V, which causes the following problem. If the power source potential V.sub.EE is higher than -2.2 V, then no current flows in the current switch S1 for a while, where two outputs OUT and /OUT, which must be differential, both remain in the HIGH level. Therefore, the conventional differential ECL circuit cannot ensure stable operations unless the power source potential V.sub.EE is lower than -2.2 V, and therefore needs an additional power source for generating the power source potential V.sub.EE in addition to the power source for generating the a terminal voltage V.sub.TT (=-2 V).
As reviewed above, there is a difficulty in maintaining stable operations required as a stable logic circuit by applying a typical ECL-level signal to a differential ECL circuit and by using a low voltage power source of approximately -2 V to activate the circuit. Not only for differential ECL circuit, the above discussion essentially applies also to single-end ECL circuits in which only structural difference lies in fixing one of input signals to a predetermined potential (typically, -1.3 V).